The present invention generally relates to phase-locked loop (PLL) circuits, and more particularly to a PLL circuit which has a function of a frequency multiplier and which can produce an output signal having little jitter.
Conventionally, in a PLL circuit having a function of a frequency multiplier, an input signal e.sub.i (t) is supplied to a phase detector, and the phase detector compares the phase of the input signal with the phase of an output signal e.sub.o (t) of a voltage controlled oscillator (VCO) which will be described later. The phase detector produces an error signal e.sub.r (t) and supplies it to a loop filter. The loop filter filters off the noise and higher frequency component in the error signal e.sub.r (t) to produce an error voltage Er. The error voltage Er is applied to the VCO as a control voltage to variably control the frequency and phase of an output oscillating signal e.sub.o (t) of the VCO.
The frequency of the oscillating signal e.sub.o (t) of the VCO is set to a predetermined value higher than the frequency of the input signal e.sub.i (t). The oscillating signal e.sub.o (t) is fed back to an input of the phase detector through a frequency divider on the one hand, and is supplied to an output terminal on the other hand.
A PLL circuit having a function of a frequency multiplier has a feedback loop constituted by the phase detector, the loop filter, the VCO, and the frequency divider functions as well known. Hence, the VCO supplies to the output terminal a signal e.sub.o (t) which has a phase synchronized with the phase of the input signal e.sub.i (t) and whose frequency is a multiplication of the frequency of the input signal e.sub.i (t) by a frequency dividing ratio of the frequency divider.
The error signal e.sub.r (t) is given by an equation. EQU e.sub.r (t)=K.sub.c (.theta..sub.i (t)-K.sub.d .theta..sub.o (t))(1)
where Kc is the gain factor (expressed in volt/radian) of the phase detector, .theta..sub.i (t) is the phase of the input signal e.sub.i (t), Kd is the gain factor of the frequency divider, and .theta..sub.o (t) is the phase of the output signal e.sub.o (t) of the VCO.
The error signal e.sub.r (t) is converted into an error voltage E.sub.r by the loop filter. When the loop filter has a transfer function F(s) where s is a Laplace transform operator, E.sub.r (s), F(s) and C.sub.r (s) are related as follows. EQU E.sub.r (s)=F(s)e.sub.r (s) (2)
The following equation is obtained by applying the Laplace transform to the equation (1). EQU e.sub.r (s)=K.sub.c (.theta..sub.i (s)-K.sub.d .theta..sub.o (s))(3)
The output oscillating frequency of the VCO is controlled by the error voltage E.sub.r, and the variation .DELTA..omega. in the output oscillating frequency is given by EQU .DELTA..omega.=K.sub.o E.sub.r ( 4)
where K.sub.o is the gain factor of the VCO expressed in radian/volt second. Since the frequency is the time derivative of the phase, the equation (4) can be rewritten as d.theta..sub.o (t)/dt=K.sub.o Er. Hence, using the Laplace transform, the equation (2) is transformed into EQU s.theta..sub.o (s)=K.sub.o Er(s). (5)
From the equations (2), (3) and (5), the following equation is obtained by eliminating Er(s) and e.sub.r (s). EQU .theta..sub.o (s)/.theta..sub.i (s)=K.sub.c K.sub.o F(s)/(s+K.sub.d K.sub.c K.sub.o F(s)) (6)
.theta..sub.o (s)/.theta..sub.i (s) shown in the equation (6) is the transfer function of the frequency multiplying circuit. The natural angular frequency .omega..sub.n, dumping factor .zeta., lock range .DELTA..omega..sub.L and capture range .DELTA..omega..sub.c of the loop are known from .theta..sub.o (s)/.theta..sub.i (s).
The bandwidth of the loop is determined by the loop gain and the cut-off frequency of the loop filter in accordance with the purpose of the loop.
PLL circuit of such a construction are widely used in various applications. For example, in transmitting data through a power line, a PLL circuit of the above-mentioned type is used as a frequency multiplier to produce a carrier signal having a phase synchronized with the phase of a power.
However, those conventional PLL circuits has a disadvantage that as the multiplying factor increases, a transitory phase error becomes larger in the output oscillating signal of the VCO. This transitory phase error is generally referred to as jitter.
The jitter is constituted mainly by the l/f-noise caused by a transistor or transistors in the VCO. A part of l/f-noise which has a frequency outside the bandwidth of the loop cannot be followed by the frequency following operation of the above-mentioned PLL, and causes the jitter to take place. For this reason, if the bandwidth of the loop is widened, the jitter is reduced.
However, when the bandwidth of the loop is widened, the PLL comes to follow an alternating current component (ripple component) of higher frequency in the error signal. In such a case, the VCO is sensitive to the above-mentioned alternating current component and produces an oscillating signal that appears to undergo an angular modulation.
For these reasons, in prior art, the bandwidth of the loop is set to a halfway width such that the jitter and the angular modulation are balanced